`timescale 1ns / 1ps

module bit(
    input [3:0] digit,
    output a,
    output b,
    output c,
    output d,
    output e,
    output f,
    output g,
    output dot
    );
    reg [7:0] leds;
    always @(digit)
    begin
        case (digit)
        4'b0000: leds<=8'b01111110;//0
        4'b0001: leds<=8'b00110000;//1
        4'b0010: leds<=8'b01101101;//2
        4'b0011: leds<=8'b01111001;//3
        4'b0100: leds<=8'b00110011;//4
        4'b0101: leds<=8'b01011011;//5
        4'b0110: leds<=8'b01011111;//6
        4'b0111: leds<=8'b01110010;//7
        4'b1000: leds<=8'b01111111;//8
        4'b1001: leds<=8'b01111011;//9
        4'b1010: leds<=8'b00000001;//-
        default: leds<=8'b0;//blank
        endcase
    end
    assign {dot,a,b,c,d,e,f,g} = leds;
endmodule
